Field of the Invention
The present invention relates to a shift register and, more particularly, to a shift register capable of performing stable operation.
Discussion of the Related Art
A shift register sequentially outputs a plurality of scan pulses and, as such, sequentially drives gate lines of a display device such as a liquid crystal display (LCD) device.
To this end, such a shift register includes a plurality of stages to sequentially output scan pulses.
FIG. 1 is a circuit diagram illustrating a configuration of a stage applied to a conventional shift register. FIG. 2 is a timing diagram depicting waveforms of input and output signals of the stage applied to the conventional shift register of FIG. 1. FIG. 3 is a diagram illustrating characteristics of a relationship between gate voltage and drain current according to temperature of a conventional oxide semiconductor transistor. FIG. 4 is a timing diagram depicting waveforms when the conventional shift register of FIG. 1 operates normally and abnormally.
Generally, a shift register includes a plurality of stages. An output signal ‘Vout’ output from each stage is a scan signal ‘SS’ to be transferred to gate lines formed at a panel.
The scan signal ‘SS’ includes a scan pulse having a turn-on voltage capable of turning on a switching element of each pixel connected to each gate line, and a turn-off signal for maintaining the switching element in an off state for a remaining period of one frame.
Generally, each of the stages outputs the scan pulse once during one frame and, as such, the scan pulse is output in a sequential manner from the stages.
As shown in FIG. 1, each of the stages includes a pull-up switching element T6 to be turned on or off in accordance with the logic state of a Q-node, and to receive a first clock signal CLK1 in an on state, thereby outputting the scan pulse, a pull-down switching element T7 to be turned off when the pull-up switching element T6 is turned on, and to be turned on when the pull-up switching element T6 is turned off, thereby outputting the turn-off signal, and a Q-node control switching element T2 connected between the Q-node and a discharge voltage source ‘VSS’, to be controlled by a control signal.
Each stage may include at least one element performing the function of the Q-node control switching element T2.
Generally, the control signal, which is input to a gate of the Q-node control switching element T2, is maintained in a low level state when the Q-node is in a high level state.
That is, when a high-level signal A is input to the Q-node, the pull-up switching element T6 is turned on and, as such, the scan pulse is output. In this case, no discharge voltage from the discharge voltage source ‘VSS’ is supplied to the Q-node control switching element T2 unless the Q-node control switching element T2 is turned on.
When the scan pulse is output, the high-level control signal A is input to the gate of the Q-node control switching element T2 and, as such, the Q-node control switching element T2 is turned on. In this case, the discharge voltage is supplied to the gate of the pull-up transistor T6, thereby turning off the pull-up transistor T6. As a result, the scan pulse is not output from the pull-up transistor T6.
In the case of a shift register constituted by only N-type transistors, it may be impossible to lower the voltage at a certain node below the discharge voltage of the discharge voltage source ‘VSS’. For at least this reason, even when a transistor, the gate of which is connected to the node, is in a logically off state, leakage current flows through the transistor because a gate-source voltage ‘Vgs’ of the transistor is above 0.
In particular, when the threshold voltage of the transistor is negative, leakage current is increased and, as such, the circuit may operate abnormally.
Similarly, in the stage shown in FIG. 1, for the same reason as mentioned above, some of the charges supplied to the Q-node to turn on the pull-up transistor T6, namely, charges B, may leak to the discharge voltage source ‘VSS’ via the Q-node control switching element T2. In this case, the stage may operate abnormally.
The above-mentioned reason will be described in detail with reference to FIGS. 2 to 4.
When an N-type oxide semiconductor transistor is employed in the shift register, it is preferred that the threshold voltage of the transistor be positive. However, the threshold voltage of the transistor is varied in a negative direction in accordance with an increase in temperature, as shown in FIG. 3. The threshold voltage of the transistor may be varied in a negative direction for various reasons other than temperature.
In this case, the N-type oxide semiconductor transistor T2, which should be turned off in a period that the scan pulse is output from the stage, may not be turned off and, as such, leakage current may be generated. Due to such leakage current, the voltage at a set node may be lowered and, as such, a normal output may not be generated from the stage.
When no leakage current is generated from the Q-node control switching element T2, a start signal ‘Vst’ is supplied to the stage, as shown in FIGS. 2 and 4(a). In this case, when the scan pulse ‘SS’ (‘Vout’) is output from the stage, the Q-node signal supplied to the Q-node is normally boot-strapped by the scan pulse ‘SS’. As a result, the scan pulse ‘SS’ may be normally output.
However, when leakage current is generated from the Q-node control switching element T2, the Q-node signal supplied to the Q-node when the scan pulse ‘SS’ is generated cannot be normally boot-strapped by the scan pulse ‘SS’, as shown in FIG. 4(b). As a result, the waveform of the scan pulse ‘SS’ output from the stage is varied and, as such, the circuit driven by the scan pulse may operate abnormally.